ATA8743-PXQW【PDF 28/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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9152BINDCO02/10

ATA8743

12.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk

CPU

, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 12-4 on page 28 shows the parallel instruction fetches and instruction executions

enabled by the Harvard architecture and the fast access Register File concept. This is the basic

pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks, and functions per power-unit.

Figure 12-4. The Parallel Instruction Fetches and Instruction Executions

Figure 12-5 on page 28 shows the internal timing concept for the Register File. In a single clock

cycle an ALU operation using two register operands is executed, and the result is stored back to

the destination register.

Figure 12-5. Single Cycle ALU Operation

12.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate Program Vector in the Program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in Interrupts on page 66. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 the External Interrupt Request

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

rd Instruction Execute

4th Instruction Fetch

CPU

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

clk

CPU

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